FIG. 1 depicts a flip-chip packaged IC, a form factor in which the packaged IC is flipped over top-for-bottom when mounting to a printed circuit board or other substrate. In FIG. 1, IC 10 is protectively contained with a package 20 from whose lower surface there protrudes a number of raised metallic solder bumps 30. These solder bumps are electrically coupled to various components and nodes within IC 10, and are used to bring operating potential, ground, and signals into IC 10, and to bring signals from IC 10, perhaps to other ICs mounted on substrate 40. In practice, there may be many thousands of such solder bumps disposed on the lower surface of package 20.
In mounting the packaged IC, solder bumps 30 are placed in contact with pads (not shown) on the upper surface of substrate 40 to which conductive leads 50 are electrically coupled. Typically a reflow solder technique is used to simultaneously solder all of bumps 30 to the underlying corresponding pads. While this mounting technique advantageously reduces inductance between the IC and the substrate traces, a major shortcoming is that one cannot wafer probe a flip-chip die. Instead, IC testing must be deferred until fabrication is complete. The reasons for this shortcoming will now be described.
FIG. 2 is a simplified representation of a generic IC 10, which is shown as including a logic circuit 60 and a controller circuit 70 fabricated on a "layer" 80. In reality, "layer" 80 comprises a great many layers, e.g., a semiconductor substrate layer that includes regions of dopant deposition, layers of oxide, layers of metallization and so forth. The various circuits comprising IC 10 may be fabricated using metal-oxide-semiconductor ("MOS") or complemental MOS (CMOS").
Shown on "layer" 80 are conductive traces 90 that can make electrical connection to one or more conductive vias that are normal to the plane of "layer" 80. Vias 100 make electrical connection to an overlying uppermost layer 110 of metallization (often called "metal-one") upon which are found various conductive traces 120. Not shown in FIG. 2 for ease of illustration is a power grid mesh layer that typically underlies the metal-one layer and provides a plurality of VCC and ground traces, according to vendor specification. These traces are via-coupled down to the IC, and are coupled upward to appropriate sites on the destination layer.
Signal carrying traces on the metal-one layer are perhaps 1 .mu.m in width, while power carrying traces on the mesh layer (not shown) may be 100 .mu.m wide, or greater, depending upon vendor specifications. In practice, some on the traces shown on "layer" 80 may in fact be formed on the metal-one layer.
Vias 100 can continue vertically upward through an insulating typically oxide layer 130 to a distribution layer 140. (Layer 130 is shown transparent, for ease of illustration.) Conductive landing sites 150 are formed on the distribution layer, to which sites are affixed the solder bumps 30 that are seen in FIG. 1. The upper left corner of FIG. 2 shows a few of the solder bumps spaced-apart from the distribution layer landing sites, for ease of understanding. Typically the size of landing sites 150 is perhaps 10 .mu.m.times.10 .mu.m, and while the sites will typically be formed in an array, it is not necessary that a site be located at every position in the array. It is understood that the configuration of FIG. 2 is packaged and then flipped top-for-bottom before mounting, as shown in FIG. 1.
Among the potentially thousands of landing sites 30 will be one or more sites to bring operating potential VCC to IC 10, e.g., landing site 30-VCC, one or more sites to bring ground to IC 10, e.g., landing site 30-GND, and one or more sites used optionally to monitor testing of IC 10 after fabrication, e.g., landing site 30-T.
A controller 70 is often included in ICs to implement on-chip testing of the fully fabricated IC. Unfortunately prior art flip-chip architecture does not permit wafer probe testing because landing sites 150 are simply too small (e.g., 10 .mu.m.times.10 .mu.m) to be contacted by pins on a wafer probe. (A wafer probe requires a target contact area sized to at least about 70 .mu.m.times.70 .mu.m.)
Thus, testing of IC 10 can occur only after packaging is complete, with VCC power, ground, and test signals coupled to the IC through bumps 30 on the destination layer 140. Simply stated, until fabrication is complete and the distribution layer is in place, one cannot bring VCC or ground or test signals into or out of the integrated circuit. One cannot test before fabricating the destination layer because the surface of vias 100 that would be available through the insulation layer 130 are simply too small (e.g., perhaps only 1.4 .mu.m.times.1.4 .mu.m) to accommodate contact with pins from a wafer probe unit.
To appreciate the difficulties posed by the inability to test flip chip packaged dies until after fabrication is complete, it is necessary to recall that even a 13 mm.times.13 mm sized IC 10 die may include tens of thousands of circuits. Given the thousands of interconnections that are present in typical application specific ICs ("ASICs"), the likelihood of some interconnect layout errors can be high. Unfortunately, as is evident from FIG. 2, once the distribution layer is formed, it is impossible to change routing at the metal-one layer to correct errors or bugs in the fabricated IC because the metal-one layer is no longer accessible.
By way of example, consider logic unit 60, which includes NAND gates I-1, I-2, I-3 and a NOR gate I-4. Of course in an actual IC, there may be tens of thousands of such logic units. Assume that the circuit designer intended logic unit 60 to function as a mono-stable or one-shot. The two inputs to NOR gate I-4 were intended to be the input to NAND gate I-1 and an inverted and time-delayed version thereof, which is output from I-3.
Assume that post-fabrication testing indicates a consistent error in the output of NOR gate I-4 in logic unit 60. Given this post-fabrication testing result, the layout circuit designer suspects that a metal-one layout error is causing the error or bug in logic unit 60. Looking at the trace denoted 120-BUG on metal-one layer 110, it is believed that the source of the bug is that the INP-2 input lead to I-2 is inadvertently tied to ground, e.g., through via 100, through trace 120-BUG, through the distribution layer bump in the top row of bumps denoted 30-G. On NAND gate I-2, the pin denoted G indeed wants to be coupled to ground, but the INP-2 pin does not. Before ordering a revised layout of the metal-one trace, e.g., to sever trace 120-BUG between points A and B, it would be beneficially to actually re-test logic unit 60 with the severed trace. After all, because IC 10 could not be earlier tested, one does not know with certainty that IC 10 is not itself defective. Unfortunately, as is apparent from FIG. 2, once destination layer 140 is in place, no access to the underlying IC is possible for troubleshooting or repairs.
If access could somehow be provided, then focussed ion beam ("FIB") technology or the like could be used to break trace 120-BUG between points A and B. Once the trace were so broken, if further testing indicated that logic unit 60 (and indeed all other circuits on the IC) functioned satisfactorily, the circuit designer could with confidence order a new layout of the relevant portion of metal-one layer 110.
However, in prior art flip-chip architecture, the layout designer does not have the luxury of changing the metal-one layer once the distribution layer is in place. But until the distribution layer is fabricated, no testing to reveal metal-one layout errors can be undertaken. At best, the layout designer must use FIB (or equivalent) techniques to alter metal-one blindly, e.g., before attachment of the distribution layer and before testing the IC, and then complete fabrication. However, because the FIB-modified IC was not tested to begin with (since no testing can occur without the destination layer and full IC fabrication), the IC may be suspect, e.g., it may have defects beyond what is presently suspected to be defective.
Further, FIB removal of metal-one traces is a very time consuming operation, especially if many modifications to traces must be made. Indeed, it can take more than five hours to FIB-modify metal-one traces on a 13 mm.times.13 mm die. Once a die has been blindly selected (e.g., selected without benefit of testing), and FIB-modifications have been made, all non-modified ICs are useless, and typically are discarded. If FIB-modification results in a fully functioning IC, then changes are made on a production basis in the metal-one mask, and ICs are then mass produced. The inability to wafer probe test ICs used in flip-chip architecture results in production time delays, poor yield, and resultant higher costs to deliver mass produced ICs.
Thus, there is a need for a mechanism by which a flip-chip packaged die may be wafer probe tested, e.g., tested before fabrication of the destination layer occurs. Such a mechanism would expose the metal-one layer of such an IC to FIB or other modification and permit testing before as well as after the modification. Once a modification has been test-confirmed, the mass-produced metal-one layer pattern could be modified accordingly, with the result that substantially bug-free ICs are produced.
The present invention provides such a mechanism and a method for such testing.